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Survey of Low Power Testing of VLSI Circuits

Received: 13 April 2013     Published: 20 May 2013
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Abstract

The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. This paper surveys about the available low power testing techniques during testing. It also suggests some advantages and disadvantages associated with every techniques

Published in Science Journal of Circuits, Systems and Signal Processing (Volume 2, Issue 2)
DOI 10.11648/j.cssp.20130202.15
Page(s) 67-74
Creative Commons

This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited.

Copyright

Copyright © The Author(s), 2013. Published by Science Publishing Group

Keywords

Dft, Bist, Lfsr, Cut, Atpg

References
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  • APA Style

    P. Basker, A. Arulmurugan. (2013). Survey of Low Power Testing of VLSI Circuits. Science Journal of Circuits, Systems and Signal Processing, 2(2), 67-74. https://doi.org/10.11648/j.cssp.20130202.15

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    ACS Style

    P. Basker; A. Arulmurugan. Survey of Low Power Testing of VLSI Circuits. Sci. J. Circuits Syst. Signal Process. 2013, 2(2), 67-74. doi: 10.11648/j.cssp.20130202.15

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    AMA Style

    P. Basker, A. Arulmurugan. Survey of Low Power Testing of VLSI Circuits. Sci J Circuits Syst Signal Process. 2013;2(2):67-74. doi: 10.11648/j.cssp.20130202.15

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  • @article{10.11648/j.cssp.20130202.15,
      author = {P. Basker and A. Arulmurugan},
      title = {Survey of Low Power Testing of VLSI Circuits},
      journal = {Science Journal of Circuits, Systems and Signal Processing},
      volume = {2},
      number = {2},
      pages = {67-74},
      doi = {10.11648/j.cssp.20130202.15},
      url = {https://doi.org/10.11648/j.cssp.20130202.15},
      eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.cssp.20130202.15},
      abstract = {The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. This paper surveys about the available low power testing techniques during testing. It also suggests some advantages and disadvantages associated with every techniques},
     year = {2013}
    }
    

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    T1  - Survey of Low Power Testing of VLSI Circuits
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    T2  - Science Journal of Circuits, Systems and Signal Processing
    JF  - Science Journal of Circuits, Systems and Signal Processing
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    AB  - The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. This paper surveys about the available low power testing techniques during testing. It also suggests some advantages and disadvantages associated with every techniques
    VL  - 2
    IS  - 2
    ER  - 

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Author Information
  • Department Of Ece, Kongu Engineering College, Perundurai, Tamil Nadu, India

  • Department Of Ece, Kongu Engineering College, Perundurai, Tamil Nadu, India

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